The present invention relates to a semiconductor integrated circuit device in which a volatile memory, such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), and an electrically rewritable or reprogrammable nonvolatile memory, such as a flash memory, are packaged together with a control processing unit, such as a central processing unit, over a semiconductor substrate; and, more particularly, the invention relates to a repair technique which is effective when applied to an on-chip type large-scale integrated circuit, such as a DRAM-consolidated LS1 (Large-Scale Integration), a DRAM-embedded LS1 or a system LS1.
Nowadays, the large scale of a semiconductor integrated circuit device is in the category of a system on-chip, such as a DRAM-consolidated LSI, a DRAM-embedded LSI or a system LSI.
As a semiconductor integrated circuit device is provided with a larger scale, its internal defects can be less ignored. Especially, a memory, such as a DRAM, a SRAM or a flash memory, is expected to have a relatively small area, but a large storage capacity, so that it becomes susceptible to defects caused by the remarkably fine working during manufacture and the resultant miniaturization of signals. Therefore, the application of a redundancy circuit technique to such semiconductor circuit devices is important so that an expected system operation can be achieved irrespective of the occurrence of more or less defects.
For enlarging the scale of a semiconductor integrated circuit device, it is frequently desirable to apply a trimming technique for achieving the desired circuit characteristics. By this trimming technique, an analog amount, such as an internal voltage or current, and a quasi-analog amount, such as the timing of a timing signal, can be sufficiently brought to a desired value irrespective of the manufacturing dispersion of the semiconductor integrated circuit device.
The redundancy circuit technique and the trimming technique for a large-scale semiconductor integrated circuit device are well-known. One such technique is disclosed in Japanese Patent Laid-Open No. 334999/1995, and in corresponding U.S. Pat. No. 5,561,627, of Hitachi, Ltd., and is used in a program for providing defect repair information using the memory cells of an electrically reprogrammable nonvolatile memory, such as a flash memory. In this technique, repair information specifying a defective memory cell in the nonvolatile memory is stored in the memory cell of the nonvolatile memory; the repair information is latched in an internal latch circuit at the time of initialization, and the latched repair information and an access address are compared so that the access is replaced, in the case of coincidence, by the access to a redundant memory cell.
On the other hand, another technique is disclosed in Japanese Patent Laid-Open No. 214496/1998, and in corresponding U.S. patent application Ser. No. 09/016,300, of Hitachi, Ltd., and in which trimming information is stored for use in the storage region of a portion of a nonvolatile memory, such as a flash memory. In accordance with this technique, more specifically, there is provided a trimming circuit for finely adjusting the output clamp voltage of voltage clamp means for providing an operating power source for the flash memory so that the trimming information for determining the state of the timing circuit is programmed in the memory cells of the flash memory. The programmed trimming information is read out in a reset operation from the flash memory and is internally transferred to a register. The state of the trimming circuit is determined by using the transferred trimming information. As a result, the clamp voltage to be outputted from voltage clamp means is trimmed to a value suitable for the operation of the flash memory, thereby compensating for the manufacturing dispersion of the semiconductor integrated circuit device.
An example of a system LSI is described on pp. 34 to 38 of “Electronic Materials” (issued in January, 1998, by Kabushiki Gaisha Kogyo Chosakai), wherein, as seen in FIG. 4 thereof, a volatile memory, such as a flash memory, and a DRAM are consolidated together with a CPU (Central Processing Unit). The technique for forming the nonvolatile memory and the DRAM by a common process is already described in U.S. Pat. No. 5,057,448. On the other hand, examples of a semi conductor integrated circuit device packaging a flash memory and a DRAM together with a CPU on one semiconductor substrate are described in Japanese Patent Laid-Open Nos. 52293/1989 and 124381/1998.